Need Suggestions for Riscv CPU

1 stanley0306 2 5/15/2025, 3:37:19 PM github.com ↗

Comments (2)

stanley0306 · 6h ago
I recently completed a RISC-V CPU with a 5-stage pipeline (IF, ID, EX, MEM, WB) using Verilog. It supports arithmetic (add, sub, mul), branching, memory access, and can execute C code compiled with GCC. GitHub repo: https://github.com/SHAOWEICHEN000/RISCV_CPU

I’d love feedback or suggestions for optimization / synthesis. Please click in and give me some advice

pvg · 6h ago
You could turn this into a Show HN post which will probably get better feedback - take a look at https://news.ycombinator.com/showhn.html