Need Suggestions for Riscv CPU

I recently completed a RISC-V CPU with a 5-stage pipeline (IF, ID, EX, MEM, WB) using Verilog. It supports arithmetic (add, sub, mul), branching, memory access, and can execute C code compiled with GCC. GitHub repo: https://github.com/SHAOWEICHEN000/RISCV_CPU

I’d love feedback or suggestions for optimization / synthesis. Please click in and give me some advice