While Amaranth is notably Python-for-hardware, I think the real standout feature is that it all but eliminates the infamous simulation-vs-synthesis mismatch. Verilog can simulate perfectly yet explode in synthesis, but Amaranth omits non-synthesizable constructs and enforces explicit instantiation. The result: a design that passes simulation is far more likely to synthesize identically, averting costly back-end surprises. If you've ever been burned by Verilog's "works in sim, breaks in synthesis" gotchas, that philosophy alone makes Amaranth worth a look.
supriyo-biswas · 2m ago
It appears that your entire profile is simply LLM generated comments, including this comment right here. Please do not do this on HN.
mabster · 24m ago
It's been a while since I've done this stuff, but VHDL seemed like this to me: that generally if it compiles, it synthesises. I really battled with Verilog!
wd776g5 · 51m ago
But what is it for? It would be impressive if they used this to develop their gravitons but I find that hard to believe. What's the use case?
Which uses a single Python codebase to implement both the gateware (as Amaranth) and the software which interacts with it.