Efficient Computer's Electron E1 CPU

12 LorenDB 1 7/24/2025, 3:10:04 PM morethanmoore.substack.com ↗

Comments (1)

topspin · 20h ago
The core idea:

"Instead of instructions flowing through a centralized pipeline, the E1 pins instructions to specific compute nodes called tiles and then lets the data flow between them. A node, such as a multiply, processes its operands when all the operand registers for that tile are filled. The result then travels to the next tile where it is needed. There's no program counter, no global scheduler."

A key detail:

"The compiler statically schedules each title to be what it needs to and route the data."

And

"Each tile even has a small cache of recent configurations, so loops and repeating patterns don't force a full reload every time."

A silicon dataflow engine, programmed by a complier. FPGA-like, except the "tiles" are not reprogrammable, and they should operate at far higher frequency.

Interesting. The model does seem like it's feasible without a fantasy compiler.

We'll see I suppose. Make cheap dev kits. Except (from Efficient's blog):

"Participants in the E0 DevKit Early Access Program won’t just receive hardware. They’ll engage directly with the Efficient engineering team through a collaborative, hands-on process designed to optimize their application model and software to operate on an E0-based platform that unlocks extreme efficiency for existing use cases and enables entirely new use cases."

Ouch. Not what I'd like to see.