Flexing RISC-V Instruction Subset Processors (RISPs) to Extreme Edge

4 PaulHoule 1 5/28/2025, 12:21:28 PM arxiv.org ↗

Comments (1)

brucehoult · 4h ago
It appears I may have had some influence on this project.

I've talked about finding a minimal subset of RV32I in posts in several places, including on /r/riscv, /r/asm, eevblog, probably Hacker News.

The first place was /r/asm, I developed the ideas over a few comments in July 2022...

https://www.reddit.com/r/asm/comments/w0cug7/basic_risc_inst...

The authors have come up with a slightly different subset, in particular instead of having `xor` using `xori` which can implement `not` directly and be combined with `and` to produce `nand` and thence any other boolean function, including (with quite a few instructions .. 8?) `xor`. I'm not sure this is an improvement, as if you have `xor` then `xori dst,src,imm` can be replaced with simply `li dst,imm; xor dst,dst,src`

Anyway, 28 months later /u/kowshik1729 popped up in that thread, asking how to implement use of such a restricted instruction set in gcc. I suggested the use of asm macros to emulate missing instructions as a stop-gap, which is the approach taken in this paper.

I wonder whether paper co-author Kowshik Gudimetla could be /u/kowshik1729?? If so, it might have been nice to be included in the references.

Also, coincidentally enough, one of their test programs is my primes benchmark :-)