U.S. government takes 10% stake in Intel (cnbc.com)
604 points by givemeethekeys 6d ago 718 comments
Claude Sonnet will ship in Xcode (developer.apple.com)
459 points by zora_goron 17h ago 362 comments
Condor RISC-V Performance core with novel Gantt chart work scheduling
3 childintime 1 8/29/2025, 2:19:08 PM servethehome.com ↗
Comments (1)
dlcarrier · 2h ago
It's interesting that a high-performance computing core has added instructions for bit manipulation. They're really common on low-power embedded cores, where bit manipulating inputs and outputs is more common. They can save a lot of instructions when needed, though. For example, clearing a bit in a variable, without an express instruction, requires raising two to the power of the bit, inverting the result, anding that with the variable, then writing the result back to the variable. Depending on the language, it looks something like this:https://en.wikipedia.org/wiki/Grawlix) than instructions, as though yelling pejoratives at the bit is what clears it.
The series of bitwise operators looks more grawlix (